A flip-flop or a latch circuit may be used to form a synchronizing circuit (hereinafter generally referred to as a register). A clock signal is typically supplied to the register for synchronization. However, when the number of registers is large, the capacitance load on the clock signal can affect operating speeds. In order to disperse the load of the clock signal, a buffer cell may be interposed between a clock signal supply source and the register. The buffer cell can be driven at a relatively low speed and may form a clock “tree” so that a clock signal does not drive too large a load. In this case, a gated clock system may be used. In a gated clock system a gate function that can mask the clock signal is added to the clock tree. The gate function masks the clock signal in a period of time that the clock signal is not required in the functional specification of a semiconductor integrated circuit.
A scan test method can be used to allow the semiconductor integrated circuit to be more efficiently tested. In a scan test method, registers in the semiconductor integrated circuit are connected in series (scan chain) and operate as a shift register. By doing so, data can be held or captured in the registers and then scanned off the semiconductor integrated circuit and compared with expected test data values on a tester.
Referring now to FIG. 5, a circuit schematic diagram of a conventional scan test circuit is set forth and given the general reference character 500. Conventional scan test circuit 500 is an example in which a gated clock system is applied to a scan test circuit.
Conventional scan test circuit 500 includes a multiplexer flip-flop (hereinafter referred to as a “scan FF”) 1, an AND gate 4, a level latch 2, an OR gate 3 and an AND gate 5.
AND gate 4 receives a CLK signal and a SCANTEST signal and provides an output to a control input C of level latch 2. AND gate 4 provides an output based on an AND of CLK signal and an inversion of SCANTEST signal. Level latch 2 receives an Enable signal at an input D and provides an output Q1 to an input of OR gate 3. Level latch 2 functions as a hold time assuring transparent latch that latches the Enable signal.
OR gate 3 receives SCANTEST signal at another input and provides an output to an input of AND gate 5. AND gate 5 receives CLK signal at another input and provides an output to a clock terminal CLK of scan FF 1. Scan FF 1 receives a SCANIN signal, DATAIN signal, and a ScanEnable signal and provides an output Q2. Scan FF 1 functions as a scan register.
Enable signal can have a phase different from the CLK signal. Level latch 2 provides the Enable signal at a time of a trailing edge of the CLK signal during normal operation and holds Enable signal when CLK signal is high. In this way, output Q1 is not changed during the period that CLK signal is high and a gated clock signal can be supplied to the clock terminal CLK of scan FF 1 without glitches.
OR gate 3 and AND gate 5 function to supply the CLK signal to the clock terminal CLK of scan FF 1 so that the CLK signal is masked with output Q1 of level latch 2 in the normal operation and the CLK signal propagates through unchanged during the scan test.
In conventional scan test circuit 500, because the CLK signal is always supplied to scan FF 1 during the scan test, a capture operation that receives the DATAIN signal from, for example, a combination circuit and a shift operation that receives the SCANIN signal from a register that is one stage earlier in the scan chain can be executed by switching the ScanEnable signal.
However, an Enable signal is also output from the combination circuit. In a test operation conventional scan test circuit 500, the Enable signal is not captured and latched as data by scan FF 1 and is not provided to an external output terminal through a scan path. Thus, a failure of a logic circuit that generates the Enable signal may not be detectable. This can reduce the defect detection of the combination circuit.
If the above problem is solved by providing the Enable signal to an output terminal during a normal operation, the structure of the circuit can be complicated and the test pattern can be enlarged. Although the capacity of a memory mounted on an LSI tester is increased, the defect detection ratio is not greatly improved and a design cycle time and costs can be increased.
In view of the above discussion, it would be desirable to provide a scan test circuit which may operate to allow detection of a failure of a control signal, such as an enable signal. It would also be desirable to provide a signal path for a control signal to an output of a scan test circuit. It would also be desirable to provide a signal path for a control signal to an output of a scan test circuit that may also be used to output scan data and data provided by a combination circuit.